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iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 1/13 FEATURES o 8-/12-fold level shift to 5 V output voltage o Safe low output state with single errors o Schmitt trigger inputs with two-stage pull-down current for enhanced noise immunity with limited power dissipation o Inputs compatible with TTL and CMOS levels (1.8 V to 3.3 V to 5 V) o Current-limited and short-circuit-proof push-pull output stages o Push-pull current sources for driving FETs o Surge voltage-proof outputs up to 18 V o Ground and supply voltage monitor o Protective ESD circuitry o Temperature range from -40 to 125 C APPLICATIONS o Operation of 5 V logic level N-FETs from 3.3 V systems
PACKAGES
QFN24 (iC-MFL)
QFN28 (iC-MFLT)
BLOCK DIAGRAM
IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 EN
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8
iC-MFL
VCC
Supply- and Ground Monitor
GNDR GND
Copyright (c) 2008 iC-Haus
http://www.ichaus.com
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 2/13 DESCRIPTION iC-MFL / iC-MFLT is a monolithically integrated, 8/12-channel level adjustment device which drives N-channel FETs. The internal circuit blocks have been designed in such a way that with single errors, such as open pins (VCC, GND, GNDR) or the short-circuiting of two outputs, iC-MFL's output stages switch to a predefined, safe low state. Externally connected N-channel FET are thus shut down safely in the event of a single error. The inputs of the eight/twelve channels consist of a Schmitt trigger with a pull-down current source and are compatible with TTL and CMOS levels (1.8 to 5 V). The eight/twelve channels have a currentlimited push-pull output stage and a pull-down resistor at the output. The output stages supply an output signal of 5 V and are enabled by a high signal at pin EN. Furthermore, all stages can handle surge voltage pulses (max. 18 V, pulse width < 100 ms, max. 2 % duty cycle) at the output. iC-MFL monitors the supply voltage at VCC pin and the voltages at the two ground pins GND and GNDR. The pins GND and GNDR must be connected together externally in order to guarantee the safe low state of the output stages in the event of error. Should the supply voltage at VCC undershoot a predefined threshold, the voltage monitor causes the outputs to be actively tied to GND via the lowside transistors. If the supply voltage ceases to be applied to VCC, the outputs are tied to GNDR by pull-down resistors. If the connection between the ground potential and the GND pin is disrupted, the highside and lowside transistors of the output stages are shut down and the outputs tied to GNDR via the pull-down resistors. If on the other hand the connection between ground potential and the GNDR pin is disrupted, only the output stage highside transistors are shut down; the outputs are then actively tied to GND via the lowside transistors. Open inputs IN1...8/12 and EN are actively tied to GND by pull-down currents. The pull-down currents have two stages in order to limit power dissipation with enhanced noise immunity. When two outputs of different logic states are short circuited, the driving capability of the lowside driver predominates, keeping the connected N-channel FETs in a safe shutdown state. The device is protected against destruction by ESD.
PACKAGES
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 3/13 PIN CONFIGURATION QFN24 4 mm x 4 mm to JEDEC MO220 PIN FUNCTIONS No. Name Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 OUT1 GNDR VCC IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 EN GND OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 TP 5 V Output channel 1 (n.c.) (n.c.) Ground (Resistor) 5 V Supply Voltage Input channel 1 Input channel 2 Input channel 3 Input channel 4 Input channel 5 Input channel 6 Input channel 7 Input channel 8 (n.c.) Enable Input (n.c.) Ground 5 V Output channel 8 5 V Output channel 7 5 V Output channel 6 5 V Output channel 5 5 V Output channel 4 5 V Output channel 3 5 V Output channel 2 Thermal-Pad
The Thermal Pad is to be connected to a ground plane on the PCB. Connections between GND, GNDR and the ground plane should be conciled to system FMEA aspects.
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 4/13 PIN CONFIGURATION QFN28 5 mm x 5 mm to JEDEC MO220 PIN FUNCTIONS No. Name Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 OUT2 OUT1 GNDR VCC IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 EN GND OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 TP 5 V Output channel 2 5 V Output channel 1 Ground (Resistor) 5 V Supply Voltage Input channel 1 Input channel 2 Input channel 3 Input channel 4 Input channel 5 Input channel 6 Input channel 7 Input channel 8 Input channel 9 Input channel 10 Input channel 11 Input channel 12 Enable Input Ground 5 V Output channel 12 5 V Output channel 11 5 V Output channel 10 5 V Output channel 9 5 V Output channel 8 5 V Output channel 7 5 V Output channel 6 5 V Output channel 5 5 V Output channel 4 5 V Output channel 3 Thermal-Pad
28
27
26
25
24
23
22
1 2 3 4 5 6 7
21 20 19
MFLT code... ...
18 17 16 15
8
9
10
11
12
13
14
The Thermal Pad is to be connected to a ground plane on the PCB. Connections between GND, GNDR and the ground plane should be conciled to system FMEA aspects.
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 5/13 ABSOLUTE MAXIMUM RATINGS
Beyond these values damage may occur; device operation is not guaranteed. Item No. Symbol Parameter Supply Voltage Voltage at OUT1...8/12 Peak Voltage at OUT1...8/12 Voltage at IN1...8/12, EN Voltage at GNDR referenced to GND Voltage at GND referenced to GNDR Current in OUT1...8/12, IN1...8/12, EN Current in OUT1...8/12 Current in VCC, GND Current in GND, GNDR ESD susceptibility Operating Junction Temperature Storage Temperature Range t < 100 ms, duty cycle < 2 % HBM 100 pF discharged through 1.5 k -40 -55 t < 100 ms, duty cycle < 2 % t < 100 ms, duty cycle < 2 % Conditions Min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -10 -10 -50 -100 Max. 6 6 18 6 0.3 0.3 10 120 50 10 2 150 125 V V V V V V mA mA mA mA kV C C Unit
G001 VCC G002 V() G003 Vp() G004 V() G005 V(GNDR) G006 V(GND) G007 Imx() G008 Imx() G009 Imx() G010 Imx() G011 Vd() G012 Tj G013 Ts
THERMAL DATA
Operating Conditions: VCC = 5 V 10 % Item No. T01 T02 Symbol Ta Rthja Parameter Operating Ambient Temperature Range Thermal Resistance Chip/Ambient SMD assembly, no additional cooling areas. Conditions Min. -40 Typ. Max. 125 75 C K/W Unit
All voltages are referenced to ground unless otherwise stated. All currents into the device pins are positive; all currents out of the device pins are negative.
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 6/13 ELECTRICAL CHARACTERISTICS
Operating Conditions: VCC = 5 V 10 %, Tj = -40...125 C unless otherwise stated Item No. 001 002 Symbol Parameter Conditions Tj C Fig. Min. 4.5 (No load) iC-MFL iC-MFLT VCC = 5 V, one output at 18 V (No load) iC-MFL iC-MFLT (No load, all OUTx = hi) iC-MFL iC-MFLT V() = 18 V VCC = 5 V T < 100 ms, duty cycle < 2 % -3 1.5 -50 -6 -9 -4 -6 20 -0.3 Typ. 5 Max. 5.5 7 10 V mA mA mA mA mA mA mA mA V V Unit
Total Device VCC I(VCC) Permissible Supply Voltage Supply Current in VCC
003 004
I(VCC) I(GND)
Error Current in VCC Current in GND
005
I(GNDR)
Current in GNDR
Current Driver OUT1...8/12 101 I(OUTx) Current in I(OUTx) 102 103 104 U(OUTx) Vc()lo Vs()hi permitted voltage
100 18 -0.4
Clamp Voltage lo referenced to I() = -10 mA the lower voltage of GND, GNDR Saturation Voltage hi referenced to VCC Saturation Voltage lo referenced to GND Pull-Down Resistor at OUTx referenced to GNDR Short circuit current lo Short circuit current hi Vs()hi = VCC - V(); I() = -0.5 mA I() = -2 mA I() = 0.5 mA I() = 2 mA V(GND) > Vtr(GND) V() = 0.8 V...VCC V() = 0...VCC - 0.8 V
0.2 0.8 0.2 0.8 12 2 -6 30 3.6 -3 70 6 -2 1.1
V V V V k mA mA V
105 106 107 108 109
Vs()lo Rpd() Isc()lo Isc()hi Vsh()
Output Voltage at short circuit of At two different input signals hi two outputs and lo Clamp Voltage hi I() = 10 mA 6 -3 1.1 0.8 Vt()hys = Vt()hi - Vt()lo 0.4 V < V() < Vt()hi V() > 1.4 V VCC = 0 V, V() = 0...5.5 V 4 4 200 150 20 -10 3.7 Decreasing voltage VCC VCChys = VCCon - VCCoff 3.2 100 200 225 45
Input IN1...8/12, EN 201 202 203 204 205 206 207 208 209 301 302 303 401 402 403 404 405 Vc()hi Vc()lo Vt()hi Vt()lo Vt()hys Ipd1() Ipd2() Cin() Ileak() VCCon VCCoff VCChys Vtg()hi Vtg()lo Vtg()hys Vtr()hi Vtr()lo V -0.4 1.4 1.1 400 350 70 20 10 4.4 4.1 600 270 50 5 80 270 50 V V V mV A A pF A V V mV mV mV mV mv mV Clamp Voltage lo referenced to I() = -10 mA the lower voltage of GND, GNDR Threshold Voltage hi Threshold Voltage lo Input Hysteresis Pull-Down Current 1 Pull-Down Current 2 Input Capacitance Input Leakage Current Turn-On Threshold VCC Turn-Off Threshold VCC Hysteresis
Supply Monitor
Ground Monitor GND, GNDR Threshold Voltage hi GND Moni- Referenced to GNDR tor Threshold Voltage lo GND Moni- Referenced to GNDR tor Hysteresis Vt()hys = Vt()hi - Vt()lo Threshold Voltage hi GNDR Mon- Referenced to GND itor Threshold Voltage lo GNDR Mon- Referenced to GND itor
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 7/13 ELECTRICAL CHARACTERISTICS
Operating Conditions: VCC = 5 V 10 %, Tj = -40...125 C unless otherwise stated Item No. 406 501 Symbol Vtr()hys tp(OUTx) Parameter Hysteresis Propagation Delay, INx, EN OUTx Conditions Vt()hys = Vt()hi - Vt()lo ({INx, EN}lo hi) 90 % OUTx, ({INx, EN}hi lo) 10 % OUTx, no Cl() 1 Tj C Fig. Min. 5 40 Typ. Max. 80 200 mV ns Unit
Timing
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 8/13 ELECTRICAL CHARACTERISTICS: Diagrams
V(INx, EN)
Vt()hi
Vt()lo 0 t V(OUTx) V()hi 0.9 V()hi
0.1 V()hi 0 t tp(OUTx) tp(OUTx)
Figure 1: Propagation delays
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 9/13 DESCRIPTION OF FUNCTIONS Output characteristic of the lowside transistor The lowside output transistors at the eight/twelve channels demonstrate a resistive behavior with low voltage V(OUTx) and behave as a current sink with finite output resistance with higher voltages.
I(OUTx) [mA]
rent remains high until Vt()hi (Electrical Characteristics No. 203); above this threshold the device switches to a lower pull-down current. If the voltage falls below Vt()lo (Electrical Characteristics No. 204), the device switches back to a higher pull-down current.
I(OUTx) [mA] VCC - V(OUTx)
3.6
1
2
3
4
5
[V]
-400
-400
V(OUTx) [V]
-3
1
2
3
4
5
Figure 2: Output characteristic of the lowside transistor at OUTx Output characteristic for the highside transistor The highside output transistors at the eight/twelve channels demonstrate a resistive behavior with low voltage (VCC - V(OUTx)) and behave as a current source with finite output resistance with higher voltages. Pull-down currents In order to enhance noise immunity with limited power dissipation at inputs INx and EN the pull-down currents at these pins have two stages. With a rise in voltage at input pins INx and EN the pull-down cur-
Figure 3: Output characteristic of the highside transistor at OUTx
Ipd()
V() increasing
Ipd1()
Ipd2()
V() decreasing
Vt()lo
Vt()hi
V()
Figure 4: Pull-down currents at INx and EN
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 10/13 DETECTING SINGLE ERRORS If single errors are detected, safety-relevant applications require externally connected switching transistors to be specifically shut down. Single errors can occur when a pin is open (due to a disconnected bonding wire or a bad solder connection, for example) or when two pins are short-circuited. When two output of different logic levels are shortcircuited, the driving capability of the lowside driver will predominate, keeping the connected N-channel FETs in a safe shutdown state. With open pins VCC, GND or GNDR iC-MFL switches the output stages to a safe, predefined low state via pull-down resistors or pull-down current sources at the inputs, subsequently shutting down any externally connected N-channel FETs.
I(OUTx)
[A] I(OUTx) [A]
150
-30 k
V(OUTx) [V]
1
2
3
4
5
Figure 6: Output characteristic at OUTx with open GND pin Loss of GND potential If ground potential is not longer applied to GND, the output stages are shut down and the outputs tied to GNDR via internal pull-down resistors with a typical value of 30 k.
I(OUTx) [mA]
150
-30k
3.6
V(OUTx) 1 2 3 4 5 [V]
Figure 5: Output characteristic at OUTx with disconnected VCC supply Loss of VCC potential If the supply voltage is disconnected from VCC pin, the outputs are tied to GNDR via internal pull-down resistors of typically 30 k which form a passive path from the gate of an external switching transistor to ground. A further increase of output current may occur due to self-supply effects via the output of the iC, as indicated by the arrows in Figure 5.
V(OUTx) 1 2 3 4 5 [V]
Figure 7: Output characteristic at OUTx with open GNDR pin Loss of GNDR potential If ground potential is no longer applied to the GNDRpin, the output stage highside drivers are shut down and the outputs actively tied to GND via the lowside drivers.
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 11/13 OUTPUT VOLTAGE SURGE PROTECTION An internal protective circuitry allows for short overvoltage pulses of up to 18 V at the output stages. Puls duration and duty cycle must be less than 100 ms and 2 % respectively for absolute maximum ratings.
I(OUTx) [mA] 60 80 -150 40 60
to ground via the output resistor which has a typical value of 150 .
I(OUTx) [mA] 80
40
-150
20
V(OUTx) 20 -3 mA 3.6 mA V(OUTx) [V] 5 10 15 18 [V]
5
10
15
18
Figure 9: Surge output characteristic at OUTx with Vin = high The output characteristic in Figure 9 corresponds to that of the highside driver as shown in Figure 3 for an output voltage V(OUTx) of up to VCC potential. At higher output voltage, the excess current is diverted to ground via the output resistor which has a typical value of 150 .
Figure 8: Surge output characteristic at OUTx with Vin = low The output characteristic in Figure 8 corresponds to that of the lowside driver as shown in Figure 2 for an output voltage V(OUTx) of up to VCC potential. At higher output voltage, the excess current is diverted
APPLICATION NOTES Driving an N-channel MOSFET One typical field of application for iC-MFL is in the operation of 5 V logic level N-FETs with microprocessor output signals of 1.8 to 5 V, as shown in Figure 10.
24V 3.3 V
IN1 IN2 OUT1
CL
OUT2
VCC
0V
3.3 V
RL
IN3 IN4 IN5 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8
Microcontroller
GND 5V
T1
IN6 IN7 IN8 EN
iC-MFL
VCC
Supply- and Ground Monitor
GNDR GND
Figure 10: Driving an N-channel MOSFET
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 12/13
This specification is for a newly developed product. iC-Haus therefore reserves the right to change or update, without notice, any information contained herein, design and specification; and to discontinue or limit production or distribution of any product versions. Please contact iC-Haus to ascertain the current data. Copying - even as an excerpt - is only permitted with iC-Haus approval in writing and precise reference to source. iC-Haus does not warrant the accuracy, completeness or timeliness of the specification on this site and does not assume liability for any errors or omissions in the materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in Hanover (Hannover-Messe). We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to.
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 13/13 ORDERING INFORMATION
Type iC-MFL
Package QFN24 QFN24
Order Designation iC-MFL QFN24 iC-MFLT QFN28
For technical support, information about prices and terms of delivery please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel.: +49 (61 35) 92 92-0 Fax: +49 (61 35) 92 92-192 Web: http://www.ichaus.com E-Mail: sales@ichaus.com
Appointed local distributors: http://www.ichaus.de/support_distributors.php

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